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preliminary: atheros confidential ? 1 data sheet ? 2000-2008 by atheros communications, inc. all rights reserved. at heros?, rocm?, 5-up?, driving the wireless future?, atheros driven?, atheros turbo mode?, and the air is cleaner at 5-ghz? are trademarks of atheros communications, inc. the atheros logo is a registered t rademark of atheros communications, inc. all other trademarks are the property of their respective holders. subject to change without notice. p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l preliminary april 2008 AR6002 rocm tm single-chip mac/bb/radio for 2.4/5 ghz embedded wlan applications general description the atheros AR6002 is the 2nd generation of the wlan rocm family. building on the advanced performance and features of the ar6001 family, the compact size and low power consumption of this single chip design make it an ideal vehicle for adding wlan to hand-held and other battery-powered consumer electronic devices. both ieee 802.11g (2.4 ghz) and 802.11a (5 ghz) standards are supported by the AR6002 family. the AR6002 supports both sdio 1.1 and gspi host interfaces. the AR6002 family includes a highly integrated, front-end module ((power amplifier, low-noise amplifier and rf switch), enabling low-cost designs with minimal external components. the rf performance, data throughput, and power consumption further improve upon the performance of the ar6001 family. advanced architecture and protocol techniques save power during sleep, stand-by and active states. fast antenna diversity is also supported, allowing optimal antenna selection on a per- packet basis. the AR6002 family supports 2, 3 and 4 wire bluetooth coexistence protocols with advanced algorithms for predicting channel usage by the co-located bluetooth transceiver. the AR6002 family provides multiple peripheral interfaces including uart, spi, i 2 c and 18 gpio pins. all internal clocks are generated from a single external crystal/oscillator. a variety of reference clocks are supported which include 19.2, 24, 26, 38.4, 40 and 52 mhz. AR6002 chips are available in wafer level chip scale packages (wlcsp) or ball grid arrays (bga) packaging . AR6002 features all-cmos ieee 802.11a/b/g or 802.11b/g single-chip client integrated pa, lna and rf switch minimizing external component count data rates of 1?54 mbps for 802.11g, 6-54 mbps for 802.11a advanced power management to minimize standby, sleep and active power host interface support for sdio and gspi security support for wps, wpa2, wpa, wapi and protected management frames support for 2.4 and 5 ghz operation in all available bands in all regulatory domains full 802.11e qos support including wmm and u-apsd standard 2, 3 and 4 wire bluetooth coexistence handshake support ieee 1149.1, jtag, test access port and boundary scan 18 fully-programmable gpio pins 16550-compliant uart spi or i 2 c for eeprom support internally generated low-frequency oscillator for low-power sleep available in 7 x 7 mm bga package with 0.5 mm pitch or wlcsp package with 0.4 mm pitch a h b i n t e r n a l b u s 802.11a/g mac 802.11a/g bb 802.11a/g radio power, clock management lf clk ref clk xtensa cpu memory controller ram rom i-port d-port 32 khz osc (optional) osc/xtal jtag uart spi/i 2 c gpio bridge console eeprom led test, ice sdio gspi mailbox dma host sdio or gspi AR6002 pa lna1 lna2 input lna2 AR6002 system block diagram www.datasheet.co.kr datasheet pdf - http://www..net/
p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 2 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 2 ? april 2008 preliminary: atheros confidential www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 3 preliminary: atheros confidential april 2008 ? 3 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table of contents 1 functional description ................. 5 1.1 overview ................................................... 5 1.2 xtensa cpu ....................................... 5 1.3 virtual memory controller (vmc) .... 5 1.4 ahb and apb blocks ........................... 5 1.5 master si/spi control ......................... 5 1.6 gpio ....................................................... 6 1.7 leds ....................................................... 6 1.8 mbox ..................................................... 6 1.9 uart ..................................................... 6 1.10 reset control ......................................... 6 1.10.1 cpu reset ................................... 7 1.11 reset sequence ...................................... 7 1.12 power management ............................. 7 1.12.1 hardware power states ............ 7 1.12.2 sleep state management ............ 10 1.13 system clocking (rtc block) ........... 10 1.13.1 high speed clocking .............. 10 1.13.2 low-speed clocking .................. 10 1.13.3 interface clock ............................ 11 1.13.4 antenna switching ..................... 11 1.14 mac/bb/rf block ............................ 12 1.14.1 mac block ............................... 12 1.15 clock distribution, jtag, and testing .................................................. 13 1.16 cpu subsystem .................................. 14 1.17 cpu power consumption ................. 14 1.18 memory ................................................ 14 1.19 interrupts ............................................. 15 2 host interfaces ............................. 17 2.1 sdio and gspi interfaces ..................... 17 2.2 host interface address map ............. 17 2.3 mailboxes ............................................. 19 2.3.2 error conditions ......................... 19 2.4 interrupts ............................................. 19 2.4.1 AR6002 to host ........................ 19 2.4.2 host to AR6002 ........................... 19 3 radio .............................................. 21 3.1 receiver (rx) block ................................ 21 3.2 transmitter (tx) block ....................... 22 3.2.1 synthesizer (synth) block ... 22 3.3 bias/control (bias) block ................ 23 3.4 baseband block ................................... 23 3.4.1 sm block ................................... 24 3.4.2 agc block ................................... 24 3.4.3 tim block .................................... 24 3.4.4 fft and vit blocks .................... 24 3.4.5 bbb block ..................................... 25 4 electrical characteristics ............27 4.1 absolute maximum ratings ................ 27 4.2 recommended operating conditions ........................................... 28 4.3 dc electrical characteristics ............ 29 4.4 radio receiver characteristics ......... 32 4.5 radio transmitter characteristics ... 35 4.6 AR6002 synthesizer characteristics 36 4.7 typical power consumption performance ........................................ 38 4.7.1 measurement conditions for low power state ............................... 38 4.7.2 measurement conditions for continuous receive using lna1 ............................................ 39 4.7.3 measurement conditions for continuous receive using lna2 ............................................ 40 4.7.4 measurement conditions for continuous transmit using xpa 41 4.7.5 measurement conditions for continuous transmit without xpa ................................ 42 5 ac specifications ........................43 5.1 optional external 32 khz input clock timing ..................................................... 43 5.2 external 19.2/24/26/38.4/40/52 mhz reference input clock timing ......... 43 5.3 sdio/gspi interface timing ........... 44 6 pin descriptions ...........................47 7 package dimensions ...................53 www.datasheet.co.kr datasheet pdf - http://www..net/
4 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 4 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 8 ordering information ................. 55 www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 5 preliminary: atheros confidential april 2008 ? 5 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 1. functional description 1.1 overview the AR6002 is a single chip 802.11 (a, b, g) device based on the cutting edge technology. the AR6002 has large internal ram which precludes the need for external memory. it contains a dual-band radio, a mac, a cpu, power management functions, and other functions. its internal logic and boot code are designed to detect the presence of an external host and to automatically begin communicating with that host. the supported host interfaces are sdio and gspi (generic spi). see the AR6002 block diagram on page 1. the xtensa cpu communi cates directly with the ram and rom modules within the device without any caching. boot code in the rom first detects the presence of an external host. it then begins communicating with this host. the host then downloads additional code into the ram which the xtensa cpu can later execute. the AR6002 supports a total of 18 gpios. some of these gpios are shared with the uart interface as well as the si block. the si block supports both i 2 c as well as spi interfaces and can be used to communicate with external serial devices such as eeproms or programmable oscillators. 1.2 xtensa cpu at the heart of the chip is the xtensa cpu. this cpu has four interfaces: the code ram/rom interface (ibus), going to the virtual memory controller (vmc). the data ram interface (dbus), going to the vmc the ahb interface which has been translated from the cpu's internal xtensa local memory interface (xlmi) bus. this is used mainly for register accesses. jtag interface for debugging 1.3 virtual memory controller (vmc) the vmc contains 80 kbytes of rom and 184 kbytes of ram. it has three interfaces: ibus, dbus, and ahb interface. any one of these interfaces can request access to the rom or ram modules within the vmc. the vmc contains arbiters to serve these three interfaces on a first-come-first-serve basis. 1.4 ahb and apb blocks the ahb block acts as an arbiter. it has ahb interfaces from three masters: mac, mbox (from the host), and cpu. see below for more on the mbox and mac. depending upon the address, the ahb data request can go into one of the two slaves: apb block or the vmc. data requests to the vmc are generally high-speed memory requests, while requests to the apb block are primarily meant for register access. the apb block acts as a decoder. it is meant only for access to programmable registers within the AR6002?s main blocks. depending upon the address, the apb request can go to one of the eight places listed below: rf interface (apb serial block) vmc si/spi mbox gpio uart real time clock (rtc), or mac/bb the AR6002 rf module has a long-shift interface which allows the cpu to directly control its registers via apb access. hence the apb block converts 32-bit apb reads and writes by the cpu into serial transfers to the rf module. 1.5 master si/spi control the AR6002 has a master serial interface (si) that can operate in two, three, or four-wire bus configurations to control eeproms or other i2c/spi devices. multiple i2c devices with different device addresses are supported by sharing the two-wire bus. multiple spi devices are supported by sharing the clock and data signals and using separate software-controlled gpio pins as chip selects. www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 6 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 6 ? april 2008 preliminary: atheros confidential an si transaction consists of two phases: a data transmit phase of 0-8 bytes followed by a data receive phase of 0-8 bytes. the flexible si programming interface allows software to support various address and command configurations in i2c/sp i devices. in addition, software may operate the si in either polling or interrupt mode. 1.6 gpio the AR6002 has 17 gpio pins with direct software access. many are multiplexed with other functions such as uart, si, and bluetooth coexistence (see section 6 for details). each gpio supports the following configurations via software programming: input available for samp ling by a software register input triggering an edge or level cpu interrupt input triggering a level chip wakeup interrupt open-drain or push-pull output driver output source from a software register or the sigma delta pulse-width modulation (pwm) dac in addition, different sets of gpio pins have internal pull-up/down options that are software configurable. the AR6002 has one sigma delta pwm dac shared by all of the gpio pins. it allows the gpio pins to drive intermediate output voltage levels for functions such as led dimming. the dac has a period of 256 samples with a configurable number of clock cycles per sample. by programming a register, software can control the duty cycle of the sigma delta pwm dac, approximating an intermediate voltage level. 1.7 leds the AR6002 can drive leds using gpio pins. an external npn transistor can provide higher power drive. note that the led connects to the battery voltage. for multiple led groups, multiple gpios can be assigned. the gpio sigma delta pwm dac can provide a continuous dimmer function. 1.8 mbox the mbox is a service module to handle one of two possible external hosts: sdio or gspi. the AR6002 can handle only one of these hosts at any given time. the type of host the AR6002 uses depends upon the polarity of some package pins upon system power-up. the mbox has two interfaces: an apb interface for access to the mbox registers and an ahb interface which is used by the external host to access the vmc memory or other registers within the AR6002. 1.9 uart the AR6002 includes a high-speed universal asynchronous receiver /transmitter (uart) interface that is fully compatible with the 16550 uart industry standard. unlike standard rs232 modules, AR6002's uart interface supports the transfer of multiple bytes of data between the cpu and the uart. this reduces the bandwidth requirements on AR6002's cpu when it communicates with the uart. the uart supports: polling and interrupt modes full duplex buffer system with 16-byte tx/rx fifos 5-, 6-, 7-, or 8-bit characters 1-, 1 1/2-, or 2-stop bit generation odd, even, or no parity. data rates of: ? 57600 bps ? 38400 bps ? 28800 bps ? 19200 bps ? 9600 bps ? 4800 bps ? 2400 bps 1.10 reset control the AR6002 chip_pwd_l or the sys_rst_l pins can be used to completely reset the entire chip. after these signals have been de-asserted, the AR6002 waits for the host power enable signal to be asserted by the external host processor. until this signal is asserted, the mac, bb, and soc blocks are powered off and all modules except the host interface are held in reset. once the host_pwr_en signal has been asserted, then the AR6002 turns on its crystal and later on its pll. after all clocks are stable and running, the resets to all blocks are www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 7 preliminary: atheros confidential april 2008 ? 7 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l automatically de-asserted. the only resets that stay asserted are given below: warm and cold resets to the mac warm reset to the radio (the cold reset gets automatically de-asserted) the above resets are deasserted by software. all AR6002 reset control logic resides in the rtc block to ensure stable reset generation. 1.10.1 cpu reset the cpu reset is a bit different from the other resets mentioned above. there are four scenarios where the cpu reset can be asserted: 1. it can be driven form the sys_rst_l pin, de-assertion of host _pwr_en, or from a write to an internal register. 2. the cpu reset is also dependent upon the boot strap signal ejtag_sel which is latched from the gpio_17 pin upon system initialization. the ejtag_sel signal is set when there is an in-circuit emulator (ice) connected to the chip's jtag port. in this situation, it is desirable to hold the cpu in reset even after the sys_rst_l pin has been de-asserted and the rest of the chip is running. in this situat ion, the cpu reset is asserted until gpio_13 has been set (presumably by the ice). 3. it is also possible to hold the cpu in reset until the host clears an internal register. this depends upon the boot-strap signal cpu_init_rst which is latched upon system initialization from the gpio_16 pin. if cpu_init_rst is set, then the cpu will be held in reset until the host clears an internal AR6002 register. 4. the cpu can also be reset from the write that set bit-6 of the rtc_reset register. 1.11 reset sequence after a cold_reset event, the AR6002 will enter the sdio_off state and await an enable event from the host. the AR6002 cpu will not execute any instructions until after the host enables the AR6002. the typical AR6002 cold_reset sequence is shown below: 1. the host system de-asserts chip_pwd_l, if asserted (use of chip_pwd_l is optional, but must be de-asserte d to use the AR6002). 2. sys_rst_l is de-asserted. the AR6002 latches the input level on gpio-4 and gpio-5 to determine the host interface type. (use of sys_rst_l is optional but must be de-asserted if asserted.) see the host interface chapter for a table listing interface type options. 3. for sdio and gspi interface modes, the AR6002 enters the host_off state. the host then reads interface registers to determine the type of function that the AR6002 supports. 4. when the host is ready to use the wlan, it enables the AR6002 by writing to the function enable bit which sets the host_pwr_en signal. 5. the AR6002 enters the wakeup state then the soc_on state and enables the xtensa cpu to begin the boot process. software configures the AR6002 functions and interfaces. when the AR6002 is ready to receive commands from the host, it will set the function ready bit. 6. the host reads the ready bit and can now send function commands to the AR6002. 7. the cpu may continue to be held in reset under some circumstances until its reset is cleared by an external pin or when the host clears a register. see section 1.10 above. 8. the mac cold reset and the mac/bb warm reset will continue to stay asserted until their respective reset registers are cleared. 1.12 power management the AR6002 provides integrated power management and control functions and extremely low power operation for maximum battery life across all operational states by: gating clocks for logic when not needed shutting down unneeded high speed clock sources reducing voltage levels to specific blocks in some states reducing tx and rx active duty cycles lowering cpu frequency when computational load is reduced 1.12.1 hardware power states AR6002 hardware has six top level hardware power states managed by the rtc block. table 1-1 describes the input from the mac, cpu, sdio/mbox, interrupt logic, and timers that effect the power states. figure 1-1 depicts the state transition diagram. www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 8 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 8 ? april 2008 preliminary: atheros confidential table 1-1. power management states state description off chip_pwd_l pin assertion immediately brings the chip to this state sleep clock is disabled no state is preserved host_off wlan is turned off only the host interface is power on - th e rest of the chip is power gated (off) the host instructs the AR6002 to transition to wakeup by writing a register in the host interface domain embedded cpu and wlan do not retain state (separate entry) - this state can be bypassed by as serting clk_req during de-assertion chip_pwd_l non_associated_sleep only the sleep clock is operating. the high speed crystal or oscillator is disabled. cpu, mac, bb can be voltage scaled any wakeup events (host, lf-timer, gpio-i nterrupt) will force a transition from this state to the wakeup state all internal states are maintained associated_sleep only the sleep clock is operating the high speed crystal or oscillator is disabled cpu, mac, bb can be voltage scaled any wakeup events (mac, host, lf-t imer, gpio-interrupt) will force a transition from this st ate to the wakeup state all internal states are maintained wakeup the system transitions from sleep states to on the high frequency clock is gated off as the crystal or oscillator is brought up and the pll is enabled wakeup duration is prog rammable (default 3.8ms) on the high speed clock is operational and sent to each block enabled by the clock control register lower level clock gating is implemented at the block level, including the cpu, which can be gated off using the waiti instruction while the system is on. no cpu, host and wlan activities will transition to sleep states. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 9 preliminary: atheros confidential april 2008 ? 9 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l figure 1-1. AR6002 state transitions chip_pwd_l (from any state) off ~chip_pwd_l host off sys_rst_l or ~host_pwr_en (from any state) non-associated sleep xtal off associated sleep xtal off wakeup clocks gated on wakeup events: mac clock request host/mbox request lf timer expiration uart request gpio interrupt xtal_settle (~2msec) sleep criteria: cpu_sleep & ~mac_clk_req & ~host_clk_req & ~mbox_clk_req ?any host transactions? low power high power non-assoc_ sleep_en wakeup events host_pwr_en sleep criteria www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 10 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 10 ? april 2008 preliminary: atheros confidential 1.12.2 sleep state management sleep state minimize s power consumption while saving system states. in deep sleep state, all high speed clocks are gated off and the external crystal is powered off. light sleep is similar to deep sleep, but the xtal remains running for faster wakeup. for the AR6002 to enter sleep state, the mac, sdio/mbox, and cpu systems must be in sleep state. when the embedded xtensa cpu executes the waiti command, the sdio/mbox is idle and the mac system is in sleep state, the AR6002 enters the system sleep state. in sleep state, the system gates all clock trees based on ref_clk with only the sleep clock logic operating. the system remains in sleep state until a wakeup event causes the system to enter wakeup state, wait for the high frequency clock source to stabilize, and finally ungate all enabled clock trees. the cpu exits the waiti state only when an interrupt arrives, which may result from the system wakeup event. 1.13 system clocking (rtc block) the AR6002 has an rtc block which controls the clocks and power going to other internal modules. its inputs consist of sleep requests from these modules and its outputs consists of clock enable and power signals which are used to gate the clocks going to these modules. the rtc block also manages resets going to other modules with the device. the AR6002?s clocking is grouped into two types: high-speed and low-speed. 1.13.1 high speed clocking the crystal drives the primary clock source for the internal pll within the AR6002. ref_clk is the primary clock source for the analog and digital systems. it is a high-frequency clock sourced from either an external crystal or oscillator source. it is the input to the rf synthesizer for generating required frequencies for proper 802.11 operation. an on-chip pll creates the appropriate clock frequency for digital logic. when the AR6002 is in sleep state, ref_clk is not needed. to minimize power consumption, the ref_clk generator shuts down during deep sleep. if an external crystal is being used, the AR6002 disables the on-chip oscillator driver. if ref_clk is coming from an external oscillator source, the AR6002 de-asserts its clk_req signal and the external clock source may shut down ref_clk. the pll output is programmable but it will usually run at one of on ly two frequencies: 320 mhz (during 802.11a mode) or 352 mhz (during 802.11 b/g mode). this base clock is divided into several clocks for the mac and bb modules. there are clocks running at 160 mhz, 80 mhz, and 40 mhz going to the mac and bb modules for 802.11a mode. (in 802.11g mode, these are running at 176 mhz, 88 mhz, and 44 mhz.) the soc clock comes from a clock divider module which divides the base clock by a programmable value. by default, this value is 8. hence in 802.11a mode (320 mhz base clock), the default soc frequency is 40 mhz and in 802.11b/g mode (352 mhz base clock), the soc frequency is 44 mhz. when the AR6002 exits sleep state, it enters wakeup state and asserts clk_req or enables its internal crystal oscillator depending on the clock configuration. the AR6002 remains in wakeup state for a programmable duration that must cover clock settling time. clk_req remains asserted in wakeup and on states. 1.13.2 low-speed clocking the AR6002 has eliminated the need for a second crystal thereby reducing system cost. instead, there is now a ring oscillator which produces a clock that is nominally running at 2 mhz, but this can depending on process and temperature. the AR6002 has an internal calibration module which produces a 32.768 khz output with minimal variation. for this, it uses the high- speed crystal input as the golden clock. typically, this crystal input is only available when the system is in the normal operating state and is shut down during network sleep. hence the calibration module can adjust for process and temperature variations only when the system is in the normal operating state. during network sleep, this module cannot adjust for variations in the ring-oscillator output. in case the output from the calibration module is not accurate enough, the AR6002 does have the capability to use an external low-speed clock source. this external clock source can be used as the sleep clock instead of the calibration module output. gpio_8 in the AR6002 can be used as the external clock source pin. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 11 preliminary: atheros confidential april 2008 ? 11 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l however, the external clock source need not run at 32 khz. it can be running at any similar low frequency. the tsf and other low frequency timers need to be programmed to match this frequency. in addition to providing the low-frequency sleep clock for the AR6002, the 2 mhz ring oscillator also runs the state machines and counters inside the AR6002's power control module (pcm). the pcm controls all power and isolation control signals for the entire chip. 1.13.3 interface clock in addition to the clocking mentioned above, there is another clock source for the AR6002. this clock is referred to as the host clock (either sdio or gspi). this clock is completely independent from those mentioned above and is driven by the external host to communicate with the AR6002 this clock drives the interface logic as well as a few registers which can be accessed by the host. this allows this host to probe some AR6002 information, including sdio common i/o area (cia), when the AR6002 is in sleep state. 1.13.4 antenna switching for designs that use external front-end components, the AR6002 provides the ability to control those components and the internal lna with the antenna switch table. the switch table (see table 1-2 ) contains 10 entries, each 5 bits wide, and is indexed by: the antenna selected by the mac the state of the transceiver (idle, receive, or transmit) controls for rx attenuation when fast-receive antenna diversity is enabled, the baseband will temporarily override the antenna selected by the mac once a packet has been detected. note: refer to AR6002 art reference guide for more details on switching. table 1-2. switch table chip state ant select rx atten register name idle ? ? bb_antenna_control bluetooth active ? ? bb_antenna_control tx 1 ? bb_switch_table1 rx 1 no rx 1 yes rx 1 yes tx 2 ? bb_switch_table2 rx 2 no rx 2 yes rx 2 yes www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 12 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 12 ? april 2008 preliminary: atheros confidential each 5-bit register controls the following AR6002 outputs (listed in the order of the most significant bit to the least significant bit): ante antd antc antb anta the least significant bit of the register is anta. ante, antd, antc, antb, and anta are general purpose outputs that can be used to control antenna selection and external lna, for example. for applications where the AR6002 shares an antenna with another wireless chip, antd is reserved for controlling the shared antenna switch. in normal operation, the polarity of the antenna switch settings align with the progammable switch tabl e in the baseband. for low power states, the polarity of the switch settings are shown in table 1-3 . * the polarity of antd is the same as bt_clk_en. 1.14 mac/bb/rf block the mac has an apb interface for register accesses as well as an ahb interface which is used by the mac to access memory within the vmc. 1.14.1 mac block the AR6002 wireless mac consists of five major blocks: single host interface unit (hiu), five queue control units (qcu), five dcf control units (dcu), single protocol control unit (pcu), and single dma receive unit (dru). table 1-3. switch polarity for low power states chip switch pin chip pwd host off network sleep AR6002g/x (bga package) ante low low low antd high bt_clk_en* bt_clk_en* antc low low low antb low low low anta low low low AR6002gz/xz (csp package) ante low low low antd high high high antc low low low antb low low low anta low low low www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 13 preliminary: atheros confidential april 2008 ? 13 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l figure 1-2. AR6002 wmac interface the host interface unit connects the mac to the outside world via a fixed, standardized interface. for AR6002, th e hiu is a bridge to the on-chip ahb/apb busses. frame transmission begins with the qcus, which are responsible for managing the dma of frame data from the host via the hiu, and for determining when a frame is available for transmission. each qcu feeds into (targets) exactly one dcu. ready frames are passed from a qcu to its targeted dcu. the dcu manages the vdcf channel access procedure on behalf of all qcus associated with it. once the dcu gains access to the channel, it passes the frame to the pcu, which manages the final details of sending the frame to the baseband logic. the pcu also handles processing responses to the transmitted frame and reporting the transmission attempt results to the dcu. frame reception begins in the pcu, which receives the incoming frame bit stream from the baseband logic. the pcu passes the frame data to the dru, which manages receive descriptors and transfers the incoming frame data and status to the host via the hiu. the AR6002 mac implements five qcus/ dcus, which support 802.11e method of channel access. though not required by the hardware, usually, qcu 4 is mapped to dcu4 and qcu3 to dcu3 and so on and the intent is for the five dcus to be used as follows: the highest-priority dcu is dcu 4. typically, this dcu is the one associated with beacons. the next highest priority dcu is dcu 3. typically, this dcu is the one associated with beacon-gated frames (i.e., "cab" traffic). the next highest priority dcu is dcu 2. typically, this dcu would be designated to use the hcf channel access mechanism, and all frames that are to be transmitted according to the hcf protocol would flow through this dcu. the remaining two dcus (dcu1 and dcu0) typically are us ed for normal edcf channel access, with dcu1 having higher priority over dcu0. software is responsible for mapping the eight priority levels called for in the 802.11e specification on to the two physical edcf dcus. 1.15 clock distribution, jtag, and testing the AR6002 has clock di stribution circuitry which balances all the clocks going to the bb and mac. the fundamental clock (160/176 mhz) is provided by the rf module which gets wmac dru qcu dcu arb dcu dcu qcu qcu hiu pcu www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 14 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 14 ? april 2008 preliminary: atheros confidential divided. the bb needs this fundamental clock together with several di vided versions of it. the mac requires a divided 40/44 mhz clock. in addition AR6002 has a built in jtag boundary scan of its pins. it also has features which allow for testing of the mbist modules, the rf analog-to-digital converter (adc), the rf digital-to-analog converter (dac), as well as the internal clock synthesizer. 1.16 cpu subsystem the following figure 1-3 shows the AR6002's cpu subsystem: figure 1-3. cpu subsystem the heart of the cpu subsystem consists of the xtensa core. this is a 32-bit risc core with a 5-stage pipeline and with 16-bit and 24-bit instruction encoding. the AR6002 does not utilize the tensilica instruction extension (tie) feature. the core accesses local memory space through iram interface for instructions and dram interface or data. the core can also access memory through its xtensa local memory interface (xlmi) bus. this bus is used primarily to access registers within the mac, bb, and other AR6002 functions. the module "cpu_ahb" converts this xlmi bus into a standard ahb bus. this module can buffer up to 4 write requests. when the xtensa core makes a read request, all buffered write requests are first completed in order to maintain data integrity. the cpu subsystem also has a tap controller which allows for debugging using an external jtag interface. 1.17 cpu power consumption the xtensa core power consumption can be controlled by the following means: rtc power state control: the core frequency is controlled by the real time control (rtc) module in AR6002. the xtensa core is designed to run at a maximum frequency of 60 mhz. in deep sleep mode, the voltage supply to the soc block, which includes the cpu, can be scaled down to save leakage power. refer to ?system clocking (rtc block)? on page 10 for detailed descriptions. cpu idle instruction: software can put the cpu into idle sleep state by issuing a waiti instruction. this will gate off all clocks within the cpu core. logic level clock gating: the core has been configured with several clock gating elements wh ich scale down clocks to circuitry that is not changing. 1.18 memory the AR6002 supports the following virtual and physical memory mapping. see figure 1-4 for details. tap controller cpu_ahb xtensa core jtag iram dram ahb xlmi www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 15 preliminary: atheros confidential april 2008 ? 15 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l figure 1-4. virtual and physical memory mapping 1.19 interrupts the AR6002 core supports a total of 18 interrupts. the first one (int. 0) is a software interrupt at level-1 and the second one (int. 1) is a timer interrupt at level-2. the others are hardware interrupts for various configurations. iram space dram space xlmi space 0 0x40_0000 0x80_0000 0xc0_0000 virtual memory space (12 mbytes) rom (80 k ) ram (184 k) xlmi (256k) 0 0x4_0000 0xe_0000 0xf_4000 0x10_0000 0x12_e000 0x40_0000 virtual memory space (4 mbytes) www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 16 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 16 ? april 2008 preliminary: atheros confidential www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 17 preliminary: atheros confidential april 2008 ? 17 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 2. host interfaces the AR6002 can work in various modes of io host configuration, including sdio and generic spi (gspi). table 2-1 shows pin settings for mode configuration, sampled during reset. 2.1 sdio and gspi interfaces the AR6002 interface is compliant with sdio v1.1 and supports the sdio common information area (cia) registers for identifying and initializing the AR6002. these registers include the card common control register (cccr) and function basic register (fbr) as well as cis tuple space for cis0 and cis1. all other interface communication occurs in sdio function 1 address space. figure 2-1 shows the generic sdio address map. figure 2-1 shows the generic sdio address map. 2.2 host interface address map the host sees the same address map interface regardless of the physical interface used, thus allowing the software layer above the physical interface to be identical across physical interface types. the lower 2 kb of address space must map all interface registers. the sdio and gspi interface can use mailbox aliases above 2 kb as these aliases provide larger window interfaces for increased performance. an extra 6 kb of address mapping has been added to mailbox 0 for future usage. figure 2-2 shows the host interface address map. table 2-1. pin settings for mode configuration gpio5 gpio4 configuration 00gspi mode 1xsdio mode 01reserved figure 2-1. sdio address map cccr fbr __ (function __ 1) fbr __ (function__2) fbr __ (function __ 7) ... rfu cis __ area common _ and _ per-function rfu function - unique 0x000000 - 0x0000fff 0x000100 - 0x0001fff 0x000200 - 0x0002fff 0x000300 - 0x0003fff 0x000700 - 0x0007fff 0x000800 - 0x0008fff 0x001000 - 0x0017fff 0x018000 - 0x001ffff 0x000000 - 0x001ffff cia (function 0) 128 k register space (function 1-7) window window window cis _ pointers 16 _ mb optional code storage area (csa) fbr __ (function __ 3) window www.datasheet.co.kr datasheet pdf - http://www..net/
18 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 18 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l figure 2-2. host interface address map mbox3 alias 0x2800 0x2000 mbox2 alias 0x1800 mbox1 alias 0x1000 mbox0 alias 0x800 cis window mbox3 0x600 0x400 control registers mbox2 0x300 0x200 mbox1 mbox0 0x100 0x000 window 2 kb ? 10 kb maps to sdio and gspi only (larger aliases for mbox access) 0 kb ? 2 kb maps to all interfaces host side sdio/gspi dma dma dma dma internal memory map 256 mb mbox0 alias 0x3fff 10 kb ? 16 kb extra mailbox 0 alias for future usage www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 19 preliminary: atheros confidential april 2008 ? 19 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 2.3 mailboxes the AR6002 supports four full duplex mailboxes to move messages between the AR6002 and the external host. messages include packets, control messages, or any software-defined communication. AR6002 hardware uses end of message (eom) markers to denote the end of a message that spans one or more memory descriptors on the AR6002 side. the flow control of the four mailboxes must be managed by software. to assist software flow control, hardware provides eight counters as a credit mechanism. the counters may count messages, memory buffers, packets, or any unit that software defines. the host and AR6002 cpus can read and write these counters using ordinary writes or atomic operations. counter resource use is optional. 2.3.2 error conditions if the host driver and AR6002 software lose flow control synchronization for any reason, mailbox errors conditions could arise. tx mailbox overflow if no dma descriptors are available on the AR6002 tx side, but the host still sends a message, the tx mailbox stalls the host physical interface. if the host interface remains stalled with the tx fifo full for a timeout period fifo_timeout, a timeout error occurs. an interrupt is sent to the AR6002 cpu and the host cpu. if the host status overflow bit is set, any mailbox tx bytes that arrive from the host when the mailbox is full, are discarded. when the host clears overflow interrupt, mailbox fifos return to normal operation. software must then either resynchronize flow control state or reset the AR6002 to recover. rx mailbox underflow if the host dma engine reads a mailbox that does not contain any data, the host physical interface stalls. if this condition persists for more than a timeout period, the host and the AR6002 are sent an underflow error interrupt. as long as the host status underflow bit is set, any mailbox reads that arrive when the mailbox is empty, return garbage data. when the host clears underflow interrupt, mailbox fifos return to normal operation. software must then either resynchronize flow control state or reset the AR6002 to recover. 2.4 interrupts this section summarizes how interrupts flow between the AR6002 cpu and host cpu. all interrupts can be masked by control registers. 2.4.1 AR6002 to host the AR6002 cpu writes to the interrupt register data ready rx fifo is not empty (clears on rx fifo empty) error interrupts, underflow or overflow wake up interrupt set when the AR6002 exits sleep flow control any count goes from 0 to 1 (cleared when count goes 1 to 0) option all AR6002 internal interrupts can be mapped to the host in case the host wants to take complete control of the AR6002 mac and resources 2.4.2 host to AR6002 host writes to int_wlan error interrupts (underflow or overflow) tx_cnt goes from 1 to 0 (out of descriptors) www.datasheet.co.kr datasheet pdf - http://www..net/
20 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 20 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 21 preliminary: atheros confidential april 2008 ? 21 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 3. radio the AR6002 transceiver consists of four major functional blocks (see figure 3-1 ): receiver (rx) transmitter (tx) frequency synthesizer (synth) associated bias/control (bias) 3.1 receiver (rx) block the receiver converts an rf signal (with 20 mhz bandwidth) to base band i and q outputs. the receiver is tuned to 2.4 ghz and 5.4 ghz for ieee 802.11 b/g and 802.11a signals, respectively. figure 3-2 shows the radio tx/ rx block diagram. for the 5 ghz operation, the receiver is comprised of a low noise amplifier (lna) followed by a variable gain amplifier (vga), a radio frequency (rf) mixer, an intermediate frequency (if) mixer, and a baseband programmable gain filter. for the 5 ghz operation, the receiver is implemented using the sliding if topology. for the 2 ghz operation, the receiver is comprised of two separate paths: lna1 and lna2. for the lna1 path, the receiver input is shared with the power amplifier (pa) output, thus eliminating the need for an external transmit/receive (t/r) switch. by eliminating an external t/r switch the overall cost of the final solution is reduced. for the lna2 path, the t/r switch is needed because lna2 input is not shared with the pa output. lna2 path is targeted for applications where the best receiver sensitivity is the primary objective, whereas the lna1 path is for cost sensitive applications. for the lna1 path, the receiver is comprised of an lna, an lna buffer, a vga, a direct conversion mixer and a baseband programmable gain filter. for the lna2 path, the receiver topology includes an lna, a vga, a direct conversion mixer and a baseband programmable filter. for the 2 ghz operation, the receiver is implemented using the direct conversion topology. for both 5g and 2g paths, mixers down convert the signal to baseband in-phase (i) and quadrature-phase (q) signals. the i and q signals are low-pass filt ered and amplified by the baseband programmable gain filter controlled by digital logic. the baseband i and q signals are sent to the adc. the baseband programmable gain filter is shared between the 2g and 5g paths. the dc offset of the receive chain is reduced using multiple digital to analog converters (dacs) controlled by the mac/baseband block. additionally, the receive chain can be digitally powered down to conserve power. figure 3-1. radio functional block diagram bias/control receiver frequency synthesizer transmitter rfout rfin txin control refclk rxout radio www.datasheet.co.kr datasheet pdf - http://www..net/
22 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 22 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l . 3.2 transmitter (tx) block the transmitter converts baseband i and q inputs to bands centered around 2.4 ghz and 5.4 ghz for ieee 802.11 b/g and 802.11a signals respectively. a block diagram is shown in figure 3-2 . the outputs of the dac are low pass filtered through an on-chip reconstruction filter to remove spectral images and out-of-band quantization noise. for the 5 ghz operation, the transmitter is comprised of the programmable reconstruction filter, an if mixer, an rf mixer, a preamplifier and a pa. the if mixer converts baseband signals to an intermediate frequency. the rf mixer converts the if signal into radio frequency signals, which are driven off_chip through the preamplifier and the pa. for the 5 ghz operation, the transmitter is implemented using the sliding if topology. for the 2 ghz operation, the transmitter is comprised of the programmable reconstruction filter, a direct conversion mixer, a preamplifier and a pa. for the 2 ghz operation, the transmitter is implemented using the direct conversion topology. the transmit chain can be digitally powered down to conserve power. to ensure that fcc limits are observed an d output power stays close to the maximum allowed, transmit output power is adjusted by a closed loop digitally programmable control loop at the start of each packet. the closed-loop power control can be based on an on-chip or off-chip power detector. 3.2.1 synthesizer (synth) block the radio supports an on-chip synthesizer to generate local oscillator (lo) frequencies for receiver and transmitter mixers. figure 3-3 shows the synthesizer topology. the synthesizer can use several xtals such as 19.2, 24, 26, 38.4, 40, and 52 mhz. for AR6002, the default xtal is 26 mhz. a reference circuitry generates a signal used as the synthesizer reference input. an on-chip voltage controlled oscillator (vco) provides the desired lo signal based on a phase/ frequency locked loop. the loop filter components are all integrated on-chip and can be digitally controlled. on power up or figure 3-2. radio tx/rx block diagram rf5out rf2out/ lna1in lna1 path ? 2g rx rf2in rf5in rx filter tx filter txini txinq rxouti rxoutq 5g rx 5g tx lna2 path ? 2g rx 2g tx x x x x x x x x x www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 23 preliminary: atheros confidential april 2008 ? 23 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l channel reselection, the synthesizer takes about 0.2 msec to settle. 3.3 bias/control (bias) block the bias/control block provides reference voltages and currents for all other circuit blocks (see figure 3-4 ). an on-chip bandgap reference circuit provides the needed voltage and current references based on an external 6.19 k 1% shunted to gnd resistor. 3.4 baseband block the AR6002 baseband module (bb) is the physical layer controller for the 802.11a/g air interface. it is responsible for modulating data packets in the transmit direction, and detecting and demodulating data packets in the receive direction. all processing is done at the baseband frequency. see figure 3-4 . figure 3-5. baseband module block diagram figure 3-3. radio synthesizer block diagram synthesizer reference input from crystal phase frequency detector charge pump loop filter (on-chip) vco divider channel select to local oscillator figure 3-4. bias/control block diagram bias reference resitor biasing control registers control interface from baseband ... agc front-end state machine & config. fft viterbi channel correction tx data bytes from mac, bb phy configuration rx data bytes, rssi / plcp header, radio configuration & gain control gain updates detection flags, rssi & noise-floor updates decoded data timing, band-width info time domain samples adc samples, power meas. 802.11b receiver downsampled data www.datasheet.co.kr datasheet pdf - http://www..net/
24 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 24 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l there are five major blocks within the baseband module: sm agc tim fft vit bbb described below are the major functions for each block, and how they interact with other blocks in the system. 3.4.1 sm block the sm block is the main state machine for the baseband phy. it en capsulates two major interfaces to the mac and radio modules. the mac interface is the interface that passes packet data to/from the mac layer. this is done through a dedicated 8-bit bus interface that is controlled through transmit and receive framing signals. a se parate configuration address space for the baseband block is written through the mac block, as the baseband block is not directly connected to the ahb bus. the baseband to radio interface is a low-latency shift control interface that allows the baseband module to quickly and autonomously adjust radio settings to reflect the current packet sizing and direction flow. this usually takes the form of gain updates, adc and dac on/ off settings, transmit and receive bias settings, and calibration mode configurations. for transmitted packets, the sm block also houses the ofdm and cck encoders/ modulators. these encoder/modulator blocks format the packet data from the mac, and generate symbols which are used for transmission over the air. these symbols are either converted into the frequency domain for ofdm modulation (fft bl ock), or are directly upsampled to the dac for cck modulation (front-end block). de cisions on rate and output power are directed by the mac through the use of transmit data headers. 3.4.2 agc block the agc block is responsible for two receive related functions: signal sizing and signal detection. because th e adc dynamic range does not span all possible input power levels, an automatic gain control feedback loop is designed into the radio and baseband receive data path. this feedback loop recognizes when input signals seen by the adc are either too small or too large, or even saturated. when this situation happens, the agc block requests a gain change to the radio through the sm block radio interface. because the state of current and previous gain changes usually coincide with the arrival/ departure of packets on the air, the agc block also signals detection status to the sm block, so that it can turn on necessary receiver blocks that would otherwise be idle with no signal to decode. there are two major mechanisms for this: strong signal dete ction and weak signal detection. strong signal detection simply looks for large changes in incoming signal strength, and will assume that these "strong signals" are most likely packets to try and decode. weak signal detection will correlate against known preamble sequences when gain changes are not occurring. a match with a cck or ofdm short preamble will trigger a detection flag for these types of "weak signals." 3.4.3 tim block the tim block is the time domain baseband front end for the transmitting and receiving of packets. on transmit, it is responsible for filtering and upsampling signals to a bandwidth and sampling rate appropriate to the dac. if there are any radio impairments that need to be corrected (carrier leak, etc.), they are corrected here. on receive, the tim block does all data path processing for time domain related signals. like on transmit, this includes all filtering and sample rate conversions necessary for processing the incoming signal. power measurements are performed here to aid the agc block in adc signal sizing. correlation to know preamble sequences are also done here for weak signal detection. when a detection flag is set, coarse timing acquisition and frequency correction are done in the tim block, as these functions are performed on data before translation into frequency domain signals (in the fft). 3.4.4 fft and vit blocks the fft block takes a signal sampled in time, and performs a fast fo urier transform to get frequency bins of data sampled in frequency bins. these frequency bins are used for ofdm symbol decoding. for receive packets, an estimate of the channel over the air is computed in the fft block as the long training www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 25 preliminary: atheros confidential april 2008 ? 25 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l sequence is a known sequence in the frequency domain. before symbols can be decoded, this channel estimate is inverted and applied to the incoming frequency symbols for channel correction. the viterbi soft-decision decoder is contained within the vit block, and is responsible for descrambling, deinterleaving, and decoding the symbols from the fft. for transmitted ofdm symbols, the fft block is reused and "run in reverse" to compute the inverse fast fourier transform (ifft). while running in ifft mode, the fft block takes in symbols from the sm block, and converts them to time samples that can be upsampled and filtered in the tim block. 3.4.5 bbb block the bbb block is the 802.11b receiver used to demodulate and decode cck packets in the 2.4 ghz range channels. it is a self contained unit that does not need other logic from the ofdm blocks except for some front-end (tim) filtering and down conversion. when a potential packet is dete cted by the agc block, both the ofdm receiver logic and the bbb block logic are enabled in a voting process. this process reduces potential latency penalties by running both receivers in parallel while the detection state machine (agc) tries to decide which type of protocol the incoming packet has been modulated with. this is done by comparing the relative preamble correlation power for the two protocol types. www.datasheet.co.kr datasheet pdf - http://www..net/
26 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 26 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 27 preliminary: atheros confidential april 2008 ? 27 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 4. electrical characteristics 4.1 absolute maximum ratings table 4-1 summarizes the absolute maximum ratings and table 4-2 lists the recommended operating conditions fo r the AR6002. absolute maximum ratings are those values beyond which damage to the device can occur. functional operation un der these conditions, or at any other condition beyond those indicated in the operational sections of this document, is not recommended. the AR6002 requires 3 power levels, 1.2v, 1.8v and 3v. the digital core runs off of 1.2v. the analog block requires 1.2v and 1.8v to operate. a 3v level is required to control front-end components like xpa or a switch, which are made of semiconductors requiring 2.8v or higher. if a 3v supply is available on the board, it can be tied to vdd_ant. if not, an internal regulator can be used. vcc_fem accepts voltages from 3.2v to 4.2v and provides an output regulated to 3.0v on ldo_out. a lower voltage, down to 3.0v, can be provided, but the output voltage is about 200mv below the input. if ldo is used, vdd_ant should be tied to ldo_out. note: maximum rating for signals follows the supply domain of the signals. table 4-1. absolute maximum ratings symbol (domain) parameter max rating unit dvdd12 digital 1.2v core supply -0.3 to 1.35 v avdd12 analog 1.2v core supply -0.3 to 1.35 v avdd18 analog 1.8v i/o supply -0.3 to 2.5 v dvdd_sdio sdio i/o supply -0.3 to 4.0 v dvdd_gpio0 gpio0 i/o supply -0.3 to 4.0 v dvdd_gpio1 gpio1 i/o supply -0.3 to 4.0 v dvdd_bt bt coexistence i/o supply -0.3 to 4.0 v vcc_fem battery voltage ldo input -0.3 to 4.35 v vdd_ant antenna control i/o supply -0.3 to 3.15 v rf in maximum rf input (reference to 50 input) +10 dbm t store storage temperature ?45 to 135 c esd electrostatic discharge tolerance 2000 [1] v [1]all pins except xtali (bga pin a11, csp bump 85), rf5i nn (bga pin b1, csp bump 8), and rf5inp (bga pin b1,csp bump 9). maximum rating is 1000v for xtali and 1500v for rf5inn/rf5inp. www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 28 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 28 ? april 2008 preliminary: atheros confidential 4.2 recommended operating conditions table 4-2. recommended operating conditions symbol (domain) parameter min typ max unit dvdd12 digital 1.2v core supply 1.14 1.2 1.26 v avdd12 analog 1.2v core supply 1.14 1.2 1.26 v avdd18 analog 1.8v i/o supply 1.71 1.8 1.89 v dvdd_sdio sdio i/o supply 1.71 1.8 3.46 v dvdd_gpio0 gpio0 i/o supply 1.71 1.8 3.46 v dvdd_gpio1 gpio1 i/o supply 1.71 1.8 3.46 v dvdd_bt bt coexistence i/o supply 1.71 1.8 3.46 v vcc_fem battery voltage ldo input 3.0 3.6 4.2 v vdd_ant antenna control i/o supply 1.71 3.0 3.46 v t ambient ambient temperature ?40 25 85 c www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 29 preliminary: atheros confidential april 2008 ? 29 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 4.3 dc electrical characteristics table 4-3 and table 4-4 list the general dc electrical characteristics over recommended operating conditions (unless otherwise specified). table 4-3. general dc electrical characteri stics (for 3.3 v i/o operation) symbol parameter conditions min typ max unit v ih high level input voltage 0.8 x v dd -v dd + 0.3 v v il low level input voltage ?0.3 - 0.2 x v dd v i il input leakage current without pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?10 10 a with pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?65 65 a v oh high level output voltage i oh = ?4 ma v dd ? 0.35 --v i oh = ?12 ma [1] v dd ? 0.35 --v v ol low level output voltage i ol = 4 ma - - 0.40 v i ol = 12 ma [1] - - 0.40 v c in input capacitance [2] --6-pf [1]for these pins only: sd io_data_0, sdio_data_1, sdio_data_2, sdio_data_3 [2]parameter not tested; value determined by design simulation table 4-4. general dc electrical characteri stics (for 1.8 v i/o operation) symbol parameter conditions min typ max unit v ih high level input voltage 0.8 x v dd -v dd + 0.2 v v il low level input voltage ?0.3 - 0.2 x v dd v i il input leakage current without pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?10 - 10 a with pull-up or pull-down 0 v < v in < v dd 0 v < v out < v dd ?35 - 35 a v oh high level output voltage i oh = ?2 ma v dd ? 0.35 --v i oh = ?6 ma [1] v dd ? 0.35 --v v ol low level output voltage i ol = 2 ma - - 0.3 v i ol = 6 ma [1] --0.3v c in input capacitance [2] --6-pf [1]for these pins only: sd io_data_0, sdio_data_1, sdio_data_2, sdio_data_3 [2]parameter not tested; value determined by design simulation www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 30 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 30 ? april 2008 preliminary: atheros confidential the following three figures show the power sequence operation for the AR6002. i/o supply = avdd18, dvdd_sdio, dvdd_gpio0, dvdd_gpio1, dvdd_bt, vcc_fem, vdd_ant 1.2v supply = dvdd12, avdd12 figure 4-3. reset and power cycle timing figure 4-1. power up/power down timing while asserting chip_pwd_l figure 4-2. power up/down timing while asserting sys_rst_l t a t b t c t d i/o supply 1.2v supply chip_pwd_l sys_rst_l t a t e t f t d i/o supply 1.2v supply chip_pwd_l sys_rst_l t f i/o supply 1.2v supply chip_pwd_l sys_rst_l t g www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 31 preliminary: atheros confidential april 2008 ? 31 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 4-5. timing diagram definitions ** supply valid represents th e voltage level has reached 90% level. description min ( sec) t a time between i/o supply valid** and 1.2v supply valid 0 t b time between 1.2v supply valid and chip_pwd_l deassertion 5 t c time between chip_pwd_l assertion and 1.2v supply invalid 0 t d time between 1.2v supply invalid and i/o supply valid 0 t e time between 1.2v supply invalid and sys_rst_l deassertion 0 t f length of sys_rst_l pulse 1 t g length of chip_pwd_l pulse 5 www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 32 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 32 ? april 2008 preliminary: atheros confidential 4.4 radio receiver characteristics table 4-7 and table 4-6 and table 4-8 summarize the AR6002 receiver characteristics. table 4-6. receiver characteristics for 2.4 ghz op eration (lna1 path - shared tx/rx) symbol parameter conditions min typ max unit f rx receive input frequency range 5 mhz channel spacing 2.312 - 2.484 ghz nf receive chain noise figure see note [1] -5-db s rf sensitivity 1 mbps 2 mbps 5.5 mbps 11 mbps 6 mbps 9 mbps 12 mbps 18 mbps 24 mbps 36 mbps 48 mbps 54 mbps see note [2] - - - - - - - - - - - - -95 -91 -89 -86 -90 -90 -89 -86 -83 -79 -75 -73 - - - - - - - - - - - - dbm ip1db input 1 db compression (min. gain) - - +11 - dbm iip3 input third intercept point (min. gain) - - +19 - dbm er phase i, q phase error - 1 - degree eramp i, q amplitude error - 0.5 - db r adj adjacent channel rejection 1 mbps 11 mbps 6 mbps 54 mbps 10 to 20 mhz - - - - 35 33 36 22 - - - - db trpowup time for power up (from rxon) - - 1.5 - s [1]does not include the effect of an external rf filter. [2]sensitivity performance based on the atheros reference design, which includes rf filter. no t/r switch, no external lna. port shared with the pa. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 33 preliminary: atheros confidential april 2008 ? 33 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 4-7. receiver characteristics for 2.4 ghz operation (lna2 path - separate rx) symbol parameter conditions min typ max unit f rx receive input frequency range 5 mhz channel spacing 2.312 - 2.484 ghz nf receive chain noise figure see note [1] -3.5-db s rf sensitivity 1 mbps 2 mbps 5.5 mbps 11 mbps 6 mbps 9 mbps 12 mbps 18 mbps 24 mbps 36 mbps 48 mbps 54 mbps see note [2] - - - - - - - - - - - - -97 -93 -91 -88 -92 -92 -91 -88 -85 -82 -77 -75 - - - - - - - - - - - - dbm ip1db input 1 db compression (min. gain) - - +3 - dbm iip3 input third intercept point (min. gain) - - +11 - dbm er phase i,q phase error - 1 - degree eramp i,q amplitude error - 0.5 - db r adj adjacent channel rejection 1 mbps 11 mbps 6 mbps 54 mbps 10 to 20 mhz - - - - 36 34 37 24 - - - - db trpowup time for power up (from rxon) - - 1.5 - s [1]does not include the effect of an exte rnal rf filter or tx/rx antenna switch. [2]sensitivity performance based on th e atheros reference design, which include s rf filter, tx/rx antenna switch, no external lna www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 34 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 34 ? april 2008 preliminary: atheros confidential table 4-8. receiver characteristics for 5 ghz operation symbol parameter conditions min typ max unit f rx receive input frequency range 5 mhz center frequency 4.90 - 5.925 ghz nf receive chain noise figure (max. gain) see note [1] and [2] -5.5 db s rf sensitivity 6 mbps 54 mbps see note [2] - - -92 -73 - - dbm ip1db input 1 db compression (min. gain) - +5 - dbm iip3 input third intercept point (min. gain) -+13-dbm er phase i,q phase error - 2 - degree eramp i,q amplitude error - 0.5 - db r adj adjacent channel rejection 6 mbps 54 mbps 10 to 20 mhz - - 22 5 - - db r alt alternate channel rejection 6 mbps 54 mbps 20 to 30 mhz - - 37 20 -db trpowup time for power up (from rxon) - - 1.5 - s [1]with an external lna. [2]sensitivity performance is based on the atheros reference design, which in cludes rf filter, tx/rx antenna switch, and an external lna. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 35 preliminary: atheros confidential april 2008 ? 35 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 4.5 radio transmitter characteristics table 4-9 and table 4-10 summarize the transmitter characteristics for AR6002. table 4-9. transmitter characteristics for 2.4 ghz operation symbol parameter conditions min typ max unit f tx transmit output frequency range 5 mhz center frequency 2.312 - 2.484 ghz p out without xpa: mask compliant cck output power -+8-dbm without xpa: evm compliant ofdm output power for 64 qam -+5-dbm with xpa: mask compliant cck output power -+16-dbm with xpa: evm compliant ofdm output power for 64 qam -+16-dbm sp gain pa gain step see note [1] -0.5-db a pl accuracy of power leveling loop see notes [2] [3] -+1/-1.5-db op1db output p1db (max. gain) 2.442 ghz - 12 - dbm oip3 output third order intercept point (max gain) 2.442 ghz - 19 - dbm ss sideband suppression --35-dbc ttpowup time for power up (from txon) - - 1.5 - s [1]guaranteed by design. [2]manufacturing calibration required. [3]not including tolerance of external pow er detector and its temperature variation. www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 36 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 36 ? april 2008 preliminary: atheros confidential 4.6 AR6002 synthesizer characteristics table 4-11 and table 4-12 summarize the synthesizer characteristics for the AR6002. table 4-10. transmitter characteristics for 5 ghz operation symbol parameter conditions min typ max unit f tx transmit output frequency range 20 mhz center frequency 4.9 - 5.925 ghz p out evm compliant ofdm output power for 64 qam see note [1] --2-dbm sp gain pa gain step see note [2] -0.5-db a pl accuracy of power leveling loop see note [3] -+1/-1.5 -db op1db output p1db (max. gain) 5.25 ghz - 4 - dbm oip3 output third order intercept point (max gain) 5.25 ghz - 12 - dbm ss sideband suppression - -32 - dbc tx mask transmit spectral mask at 11 mhz offset at 20 mhz offset at 30 mhz offset see note [4] - - - -22 -32 -52 - - - dbr ttpowup time for power up (from txon) - 1.5 - s [1]measured without a balun. output is single ended. [2]guaranteed by design. [3]manufacturing calibration required. [4]measured at the antenna connector port. average con ducted transmit power levels = 18 dbm at 64 qam (ofdm). system includes external pa. table 4-11. synthesizer composite characteristics for 2.4 ghz operation symbol parameter conditions min typ max unit pn phase noise (at tx_out) at 30 khz offset at 100 khz offset at 500 khz offset at 1 mhz offset - - - - ?99 ?99 ?108 ?115 - - - - dbc/hz f c center channel frequency center frequency at 5 mhz spacing [1] 2.312 - 2.484 ghz f ref reference oscillator frequency 20 ppm - 40/26 2 -mhz f step frequency step size (at rf) see note - 1 - mhz ts powup time for power up (from sleep) - - 0.2 - ms [1]frequency is measured at the tx output. [2] other supported frequencies are: 19.2, 24, 26, 38.4, 40, and 52 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 37 preliminary: atheros confidential april 2008 ? 37 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 4-12. synthesizer composite characteristics for 5 ghz operation symbol parameter conditions min. typ. max. unit pn phase noise (at tx_out) at 30 khz offset at 100 khz offset at 500 khz offset at 1 mhz offset - - - - ?91 ?91 ?100 ?107 - - - - dbc/hz f c center channel frequency center frequency at 5 mhz spacing [1] [1]frequency is measured at the tx output. 4.90 - 5.925 ghz f ref reference oscillator frequency 20 ppm - 40/26 3 -mhz f step frequency step size (at rf) see note [2] [2]5 mhz channel spacing is for the 5.725 to 5.925 ghz band. [3] other supported frequencies are: 19.2, 24, 26, 38.4, 40, and 52 mhz. -5-mhz ts powup time for power up (from sleep) - - 0.2 - ms www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 38 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 38 ? april 2008 preliminary: atheros confidential 4.7 typical power consumption performance the following tables illustrate typical, room temperature power consumption data measured on the atheros sd21 evaluation board. 4.7.1 measurement conditions for low power state t_amb = 25 oc all i/o pins except chip_pwd_l are maintained at their default polarities. dvdd12 = avdd12 = 1.2 v avdd18 = dvdd_sdio = 1.8 v dvdd_gpio0 = dvdd_gpio1 = dvdd_bt = dvdd_ant = vcc_fem = 3.3 v chip_pwd - all blocks power gated except for "power, clock management" host_off - all blocks power gated except for "power, clock management", "sdio", and "gspi." sleep - "lf clk" running; all blocks voltage scaled or power gated except for "power, clock management", "sdio", "gspi", and "gpio"; internal state is maintained. table 4-13. AR6002 typical power consumption - low power states mode chip set current consumption [ma] power consumption [mw] @1.2 v @1.8 v @3.3 v standby chip_pwd AR6002g/gz/x/xz 0.008 0.000 0.000 0.010 host_off AR6002gz/xz 0.050 0.007 0.001 0.076 AR6002g 0.050 0.012 0.019 0.144 AR6002x 0.050 0.007 0.019 0.135 sleep AR6002gz/xz 0.500 0.007 0.002 0.619 AR6002g 0.500 0.012 0.002 0.628 AR6002x 0.500 0.007 0.002 0.619 ieee ps dtim=1 AR6002gz/xz 1.750 0.707 0.042 3.51 AR6002g 1.750 0.712 0.042 3.52 AR6002x 1.750 0.707 0.042 3.51 dtim=3 AR6002gz/xz 0.917 0.240 0.015 1.58 AR6002g 0.917 0.245 0.015 1.59 AR6002x 0.917 0.240 0.015 1.58 dtim=10 AR6002gz/xz 0.625 0.077 0.006 0.91 AR6002g 0.625 0.082 0.006 0.92 AR6002x 0.625 0.077 0.006 0.91 www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 39 preliminary: atheros confidential april 2008 ? 39 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 4.7.2 measurement conditions for continuous receive using lna1 t_amb = 25 oc dvdd12 = avdd12 = 1.2 v avdd18 = 1.8 v dvdd_sdio = dvdd_gpio0 = dvdd_gpio1 = dvdd_bt = dvdd_ant = vcc_fem = 3.3 v table 4-14. AR6002 typical power consumption - continuous receive using lna1 path (shared tx/rx) rate [mbps] lna1 path (shared tx/rx) [-70 dbm input level] current consumption [ma] power consumption [mw] @1.2 v @1.8 v @3.3 v 163 352 146 264 352 147 5.5 68 35 2 152 11 68 35 2 152 667 352 150 967 352 150 12 68 35 2 152 18 68 35 2 152 24 69 35 2 153 36 71 35 2 155 48 72 35 2 156 54 73 35 2 158 www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 40 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 40 ? april 2008 preliminary: atheros confidential 4.7.3 measurement conditions for continuous receive using lna2 t_amb = 25 oc dvdd12 = avdd12 = 1.2 v avdd18 = 1.8 v dvdd_sdio = dvdd_gpio0 = dvdd_gpio1 = dvdd_bt = dvdd_ant = vcc_fem = 3.3 v table 4-15. AR6002 typical power consumption - continuous receive using lna2 path (separate rx) rate [mbps] lna2 path (separate rx) current consumption [ma] power consumption [mw] @1.2 v @1.8 v @3.3 v 164 282 134 264 282 134 5.5 69 28 2 140 11 69 28 2 140 667 282 138 968 282 139 12 68 28 2 139 18 69 28 2 140 24 70 28 2 141 36 71 28 2 143 48 73 28 2 145 54 73 28 2 145 www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 41 preliminary: atheros confidential april 2008 ? 41 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 4.7.4 measurement conditions for continuous transmit using xpa t_amb = 25 oc dvdd12 = avdd12 = 1.2 v avdd18 = 1.8 v dvdd_sdio = dvdd_gpio0 = dvdd_gpio1 = dvdd_bt = dvdd_ant = vcc_fem = 3.3 v table 4-16. AR6002 typical power consumption - continuous transmit using xpa rate [mbps] target output power [dbm] AR6002 current consumption [ma] xpa current consumption [ma] total power consumption including xpa [mw] @1.2 v @1.8 v @3.3 v @3.3 v 115 37 51 2 95 456 215 37 51 2 95 456 5.5 15 37 51 2 95 456 11 15 37 51 2 95 456 615 44 65 2 95 490 915 44 65 2 95 490 12 15 44 65 2 95 490 18 15 44 65 2 95 490 24 15 45 65 2 94 488 36 14 45 58 2 89 459 48 13 45 55 2 83 433 54 11 45 65 2 74 422 www.datasheet.co.kr datasheet pdf - http://www..net/
p r e l i m i n a r y : a t h e r o s c o n f i d e n t i a l 42 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 42 ? april 2008 preliminary: atheros confidential 4.7.5 measurement conditions for continuous transmit without xpa t_amb = 25 oc dvdd12 = avdd12 = 1.2 v avdd18 = 1.8 v dvdd_sdio = dvdd_gpio0 = dvdd_gpio1 = dvdd_bt = dvdd_ant = vcc_fem = 3.3 v table 4-17. AR6002 typical power consumption - continuous transmit without xpa rate [mbps] target output power [dbm] current consumption [ma] power consumption [mw] @1.2 v @1.8 v @3.3 v 1 8 38 108 2 247 2 8 38 108 2 247 5.5 8 38 108 2 247 11 8 38 108 2 247 6 8 47 108 2 258 9 8 47 108 2 258 12 8 47 108 2 258 18 8 47 107 2 256 24 8 48 107 2 257 36 7 48 105 2 254 48 6 48 104 2 252 54 4 48 102 2 248 www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 43 preliminary: atheros confidential april 2008 ? 43 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 5. ac specifications 5.1 optional external 32 khz input clock timing figure 5-1 and table 5-1 show the external 32 khz input clock timing requirements. figure 5-1. optional external 32 khz in put clock timing requirements 5.2 external 19.2/24/26/38.4/40/52 mhz reference input clock timing figure 5-2 and table 5-2 show the external 19.2/24/26/38.4/40/52 mhz reference input clock timing requirements. figure 5-2. external 19.2/24/26/38.4/40/52 mhz table 5-1. optional external 32 khz input clock timing symbol description min typ max unit ck1 frequency - 32.768 - khz ck2 fall time - - 100 ns ck3 rise time - - 100 ns ck4 duty cycle (high-to-low ratio) 15 - 85 % ck5 frequency stability ?50 - 50 ppm ck6 input high voltage 0.8*vdd_bt - vdd_bt+0.2 v ck7 input low voltage -0.3 - 0.2*vdd_bt v 1 / ck1 ck2 ck3 ck6 ck7 1 / ck1 ck2 ck3 ck6 ck7 www.datasheet.co.kr datasheet pdf - http://www..net/
44 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 44 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 5.3 sdio/gspi interface timing figure 5-3 shows the write timing for a sdio/ gspi style transaction. table 5-2. external 19.2/24/26/38.4/40/52 mhz reference input clock timing symbol description min typ max unit ck2 fall time - - 0.1 * period ns ck3 rise time - - 0.1 * period ns ck4 duty cycle (high-to-low ratio) 40 - 60 % ck5 frequency stability -20 - 20 ppm ck6 input high voltage 1.14 - 3.46 v ck7 input low voltage -0.1 - 0.3 v figure 5-3. sdio/gspi timing clock t thl t wl f pp t wh input t tlh t ih t isu output t o_dl y (max ) t o_dl y (min) v ih v il v ih v il v oh v ol shaded areas not valid www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 45 preliminary: atheros confidential april 2008 ? 45 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 5-3 shows the values for timing constraints for sdio. table 5-3. sdio timing constraints parameter description min max unit note f pp clock frequency data transfer mode 0 25 mhz 100 pf c l (7 cards) t wl clock low time 10 - ns 100 pf c l (7 cards) t wh clock high time 10 - ns 100 pf c l (7 cards) t tlh clock rise time - 10 ns 100 pf c l (10 cards) t thl clock fall time - 10 ns 100 pf c l (7 cards) t isu input setup time 5 - ns 25 pf c l (1 card) t ih input hold time 5 - ns 25 pf c l (1 card) t o_dly (min) output delay time during data transfer mode 0 14 ns 25 pf c l (1 card) t o_dly (max) output delay time during identification mode 0 50 ns 25 pf c l (1 card) www.datasheet.co.kr datasheet pdf - http://www..net/
46 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 46 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 5-4 shows the values for timing constraints for gspi. table 5-4. gspi timing constraints parameter description min max unit f pp clock frequency 0 48 mhz t wl clock low time 8.3 - ns t wh clock high time 8.3 - ns t tlh clock rise time - 2 ns t thl clock fall time - 2 ns t isu input setup time 5 - ns t ih input hold time 5 - ns t o_dly output delay 0 5 ns www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 47 preliminary: atheros confidential april 2008 ? 47 p r e l i m i n a r y : a t h e r o s c o n f i d en t i a l 6. pin descriptions this section contains a listing of the signal descriptions (see table 6-1 for the bga package pin outs). the following nomenclature is used for signal names: the following nomenclature is used for signal types described in table 6-2 : nc no connection should be made to this pin _l at the end of the signal name, indicates active low signals p at the end of the signal name, indicates the positive side of a differential signal n at the end of the signal name indicates the negative side of a differential signal ia analog input signal i digital input signal i, h input signals with weak internal pull-up, to prevent signals from floating when left open i, l input signals with weak internal pull-down, to prevent signals from floating when left open i/o a digital bidirectional signal i/o/l a digital bidirectional signal, with a weak internal pull-down oa an analog output signal o a digital output signal p a power or ground signal www.datasheet.co.kr datasheet pdf - http://www..net/
48 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 48 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 6-1. bga package pinout 123456789101112 13 a agnd rf2 outn rf2 outp rf2inp rf2in n pdet nc nc vdd18_ bias vdd12_ xtal xtali xtalo bt_clk _out b rf5inp agnd vdd18_ fe vdd12_ lna vdd12 _bias bias ref nc nc vdd12d _syn vdd12_ bb vdd18_ xtal bt_clk _en dvdd12 c rf5inn vdd12_ fe agnd agnd agnd agnd agnd gpio17 gpio16 d pa5 bias nc gpio14 gpio15 e rf5 out vdd18_ vco agnd agnd agnd agnd agnd dvss dvdd_ gpio1 dvdd_ gpio0 f vdd12_ tx5 vdd12_ synth agnd agnd agnd agnd agnd dvss dvss gpio12 gpio13 g xpa bias2 xpa bias5 agnd agnd agnd agnd agnd dvss dvss gpio10 gpiio11 h vccfe m ldo_ out agnd agnd agnd agnd agnd dvss dvss gpio9 dvdd12 j anta vddio_ ant agnd dvss dvss dvss dvss dvss dvss clk_ req dvdd12 k antc antb sys_ rst_l chip_ pwd_l l antd ante dvss dvss dvss dvss dvss dvdd12 dvdd_ sdio m agnd gpio0 gpio2 dvdd12 gpio4 gpio6 gpio8 tms tck tdo sdio_ data3 sdio_ data2 sdio_ clk n dvdd12 gpio1 gpio3 dvdd_ bt gpio5 gpio7 dvdd_ sdio dvdd12 tdi dvdd_ sdio sdio_ cmd sdio_ data1 sdio_ data0 table 6-2. signal to pin/bump mapping symbol bga pin csp bump type source or destination external pad power supply description radio anta j1 4 o antenna vdd_ant control signal for rf front end components antb k2 13 o antenna vdd_ant control signal for rf front end components antc k1 3 o antenna vdd_ant con trol signal for rf front end components antd l1 12 o antenna vdd_ant control signal for shared antenna switch ante l2 2 o antenna vdd_ant control signal for rf front end components biasref b6 35 ia - refere nce for internal analog biasing pdet a6 55 ia power detector - external power detector input rf2inn a5 37 ia rf input - 2.4ghz rf input rf2inp a4 29 ia rf input - 2.4ghz rf input www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 49 preliminary: atheros confidential april 2008 ? 49 p r e l i m i n a r y : a t h e r o s c o n f i d en t i a l rf2outn a2 10 oa rf output - 2.4ghz rf output rf2outp a3 20 oa rf output - 2.4ghz rf output rf5out e1 7 oa rf output - 5ghz rf output on AR6002x, nc on AR6002g rf5inn c1 8 ia rf input - 5ghz rf input on AR6002x, nc on AR6002g rf5inp b1 9 ia rf input - 5ghz rf input on AR6002x, nc on AR6002g xpabias2 g1 5 oa analog output - bias voltage for 2ghz external pa xpabias5 g2 6 oa digital output - bias voltage for 5ghz external pa on AR6002x, nc on AR6002g clock clk_req j12 99 o - dvdd_sdio reference clock request signal xtali a11 85 crystal input 40 mhz crystal - reference crystal interface signal xtalo a12 86 crystal output 40 mhz crystal or external clock source - reference crystal interface signal or external reference clock input digital control (bt_active, bt_freq, bt_priority, and rx_clear are now mux?d with the gpio signals) sys_rst_l k12 98 ih - dvdd_sdio full chip reset input chip_pwd_l k13 89 i - dvdd_sdio chip power down input bt_clk_en b12 96 i avdd18 input enable signal for reference clock output bt_clk_out a13 105 o - buffered reference clock output i 2 c (i2c_sclo and i2c_sdao now mux?d with the gpio signals) uart (rxdo, rxdo, uart_cts_l and uart_rts_l now mux?d with the gpio signals) gspi master (spi_ck, spi_cso_l, spi_miso, and spi_mosi now mux?d with the gpio signals) sdio sdio_clk m13 88 i - dvdd_sdio also gspi clock sdio_cmd n11 67 i - dvdd_sdio also gspi mosi sdio_data_0 n13 97 i/o - dvdd_sdio also gspi miso sdio_data_1 n12 87 i/o - dvdd_sdio also gspi host interrrupt sdio_data_2 m12 77 i/o - dvdd_sdio - sdio_data_3 m11 78 i/o - dvdd_sdio also gspi cs gspi slave : gspi pins are muxed with sdio pins gpio gpio0 m2 22 i/ol - dvdd_bt bt_priority for bluetooth coexistence table 6-2. signal to pin/bump mapping (continued) symbol bga pin csp bump type source or destination external pad power supply description www.datasheet.co.kr datasheet pdf - http://www..net/
50 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 50 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 6-3. pin/bump mapping for power supplies gpio1 n2 31 i/ol - dvdd_bt wlan_active for bluetooth coexistence gpio2 m3 11 i/ol - dvdd_bt bt_frequency for bluetooth coexistence gpio3 n3 1 i/ol - dvdd_bt bt_active for bluetooth coexistence gpio4 m5 21 i/ol - dvdd_sdio sdio/gspi interface select gpio5 n5 30 i/ol - dvdd_sdio sdio/gspi interface select gpio6 m6 39 i/ol - dvdd_sdio - gpio7 n6 49 i/ol - dvdd_sdio trst for jtag debug interface gpio8 m7 38 i/ol - dvdd_bt optional external 32khz clock input gpio9 h12 100 i/ol ? dvdd_gpio0 i2c scl or spi clock gpio10 g12 90 i/ol ? dvdd_gpio0 i2c sda or spi miso gpio11 g13 101 i/ol ? dvdd_gpio0 uart rxd or spi mosi gpio12 f12 91 i/ol ? dvdd_gpio0 uart txd or spi cs_l gpio13 f13 102 i/ol ? dvdd_gpio0 reset input for jtag interface gpio14 d12 94 i/ol ? dvdd_gpio1 uart cts gpio15 d13 103 i/ol ? dvdd_gpio1 uart rts gpio16 c13 95 i/ol ? dvdd_gpio1 - gpio17 c12 104 i/ol ? dvdd_gpio1 - digital test (ejtag_sel and trst_l are mux?d with the gpio signals) tck m9 59 ih ? dvdd_sdio jtag tck input tdi n9 58 ih ? dvdd_sdio jtag tdi input tdo m10 68 ol ? dvdd_sdio jtag tdo output tms m8 48 ih ? dvdd_sdio jtag tms input table 6-2. signal to pin/bump mapping (continued) symbol bga pin csp bump type source or destination external pad power supply description symbol bga pin csp bump type voltage description power dvdd12 n1,m4,n8, l12,j13,h13, b13 24, 32, 40, 80, 81, 82, 83 p digital 1.2v core supply vdd12_synth f2 25 p analog 1.2v core supply vdd12_tx5 f1 26 p analog 1.2v core supply vdd12_fe c2 27 p analog 1.2v core supply vdd12_lna b4 45 p analog 1.2v core supply vdd12d_syn b9 66 p analog 1.2v core supply www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 51 preliminary: atheros confidential april 2008 ? 51 p r e l i m i n a r y : a t h e r o s c o n f i d en t i a l vdd12_xtal a10 75 p analog 1.2v core supply vdd12_bias b5 - p analog 1.2v core supply vdd12_bb b10 64, 76 p analog 1.2v core supply vdd18_fe b3 28 p analog 1.8v i/o supply vdd18_vco e2 34 p analog 1.8v i/o supply vdd18_bias a9 65 p analog 1.8v i/o supply pa5biasp d1 17 p analog 1.8v i/o supply vdd18_xtal b11 84 p analog 1.8v i/o supply dvdd_sdio n7,n10,l13 50, 69, 79 p sdio i/o supply dvdd_gpio0 e13 92 p gpio0 i/o supply dvdd_gpio1 e12 93 p gpio1 i/o supply dvdd_bt n4 23 p bt coexistence i/o supply bluetooth coexistence i/o supply vcc_fem h1 33 p battery voltage ldo input battery voltage ldo input (output is 3.0 v on ldo_out) vdd_ant j2 14 p antenna control i/o supply antenna bias and control (can be tied to ldo_out) ldo_out h2 15 p battery voltage ldo output ldo output (input is vcc_fem) dvss j5,l5,j6,l6, j7,l7,j8,l8, j9,l9,e9,f9, g9,h9,f11, g11,h11,j11 41, 51, 60, 70, 71, 72, 73 p digital ground digital ground agnd e5,f5,g5,h5, e6,f6,g6, h6,e7,f7,g7, h7,e8,f8, g8,h8,e3,f3, g3,h3,j3, m1,c5,c6, c7,c8,c9,b2, a1 42, 43, 44, 52, 53, 54, 61, 62, 63 p analog ground analog ground reserved bumps nc a7, a8, b7, b8 46, 47, 56, 57 res ? note: for AR6002gz, bumps 6-8 are also no connect (nc). symbol bga pin csp bump type voltage description www.datasheet.co.kr datasheet pdf - http://www..net/
52 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 52 ? april 2008 preliminary: atheros confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 53 preliminary: atheros confidential april 2008 ? 53 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 7. package dimensions bga dimensions the bga drawing and measurements are provided in figure 7-1 and table 7-1 . the AR6002 family is available in: 7 x 7 mm, 0.5 mm pitch bga or 0.4 mm pitch wlcsp package information available separately figure 7-1. bga drawing 7 x 7 mm package www.datasheet.co.kr datasheet pdf - http://www..net/
54 ? AR6002 mac/bb/radio for embedded wlan applications atheros communications, inc. 54 ? april 2008 company confidential p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l table 7-1. bga dimensions dimension label min. nom. max. unit. min. nom. max. unit. a --- --- 1.00 mm --- --- 0.039 inches a1 0.16 0.22 0.28 mm 0.006 0.009 0.011 inches a2 0.61 0.67 0.72 mm 0.024 0.026 0.028 inches c 0.17 0.21 0.25 mm 0.007 0.008 0.010 inches d 6.90 7.00 7.10 mm 0.272 0.276 0.280 inches e 6.90 7.00 7.10 mm 0.272 0.276 0.280 inches d1 --- 6.00 --- mm --- 0.236 --- inches e1 --- 6.00 --- mm --- 0.236 --- inches e --- 0.50 --- mm --- 0.020 --- inches b 0.25 0.30 0.35 mm 0.010 0.012 0.014 inches aaa 0.10 mm 0.004 inches bbb 0.10 mm 0.004 inches ddd 0.08 mm 0.003 inches eee 0.15 mm 0.006 inches fff 0.05 mm 0.002 inches md/me 13/13 mm 13/13 inches notes: 1. controlling dimension: millimeters. 2. minimum clearance of 0.25mm between edge of solder ball and body edge. www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, inc. AR6002 mac/bb/radio for embedded wlan applications ? 55 preliminary: atheros confidential april 2008 ? 55 p r el i m i n a r y : a t h e r o s c o n f i d e n t i a l 8. ordering information the AR6002 may be ordered as follows: AR6002g-ac1e (802.11b/g bga) AR6002gz-bf1e-r (802.11b/g wlcsp) AR6002x-ac1e (802.11a/b/g bga) AR6002xz-bf1e-r (11a/b/g wlcsp) www.datasheet.co.kr datasheet pdf - http://www..net/
atheros communications, incorporated 5480 great america parkway santa clara, ca 95054 t: 408/773-5200 f: 408/773-9940 www.atheros.com company confidential subject to change without notice the information in this document has been ca refully reviewed and is believed to be accurate. nonetheless, this document is subj ect to change without notice. atheros assumes no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update or to keep current the contained information, or to notify a person or or ganization of any updates. athero s reserves the right to make changes, at any time, to improve reliability, function or design and to attempt to supply the best product po ssible. document number: 981-00059-001 mkg-0492 rev. 4 www.datasheet.co.kr datasheet pdf - http://www..net/

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